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?2004 fairchild semiconductor corporation huf76009p3, huf76009d3s rev. b1 huf76009p3, huf76009d3s 20a, 20v, 0.027 ohm, n-channel, logic level power mosfets the huf76009 is an application-specific mosfet optimized for switching when used as the upper switch in synchronous buck applications. the low gate charge and low input capacitance results in lower driver and lower switching losses thereby increasing the overall system efficiency. symbol packaging features ? 20a, 20v -r ds(on) = 0.027 ?, v gs = 10v -r ds(on) = 0.039 ?, v gs = 5v pwm optimized for synchronous buck applications fast switching low gate charge -q g total 11nc (typ) low capacitance -c iss 470pf (typ) -c rss 50pf (typ) huf76009d3s jedec to-252aa hufd76009p3 jedec to-220ab d g s gate source drain (flange) drain (flange) drain source gate ordering information part number package brand huf76009p3 to-220ab 76009p huf76009d3s to-252aa 76009d note: when ordering, use the entire part number. add the suffix t to obtain the huf76009d3s in tape and reel, e.g., HUF76009D3ST. absolute maximum ratings t c = 25 o c, unless otherwise specified symbol parameter huf76009p3, huf76009d3s units v dss drain to source voltage (note 1) 20 v v dgr drain to gate voltage (r gs = 20k ? ) (note 1) 20 v v gs gate to source voltage 20 v i d i d i dm drain current continuous (t c = 25 o c, v gs = 10v) (figure 2) continuous (t c = 100 o c, v gs = 5v) pulsed drain current 20 16 figure 4 a a a p d power dissipation derate above 25 o c 41 0.33 w w/ o c t j , t stg operating and storage temperature -55 to 150 o c t l t pkg maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s package body for 10s, see techbrief tb334 300 260 o c o c thermal specifications r jc thermal resistance junction to case, to-220, to-252 3.04 o c/w r ja thermal resistance junction to ambient to-220 62 o c/w thermal resistance junction to ambient to-252 100 o c/w note: 1. t j = 25 o c to 125 o c. caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress only ratin g and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. data sheet march 2004
?2004 fairchild semiconductor corporation huf76009p3, huf76009d3s rev. b1 electrical specifications t c = 25 o c, unless otherwise specified parameter symbol test conditions min typ max units off state specifications drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v (figure 11) 20 - - v zero gate voltage drain current i dss v ds = 20v, v gs = 0v - - 1 a v ds = 20v, v gs = 0v, t c = 150 o c - - 250 a gate to source leakage current i gss v gs = 20v - - 100 na on state specifications gate to source threshold voltage v gs(th) v gs = v ds , i d = 250 a (figure 10) 1 - 3 v drain to source on resistance r ds(on) i d = 20a, v gs = 10v (figures 8, 9) - 0.022 0.027 ? i d = 16a, v gs = 5v (figure 8) - 0.032 0.039 ? switching specifications (v gs = 5v) turn-on time t on v dd = 10v, i d = 16a v gs = 5v, r gs = 27 ?, (figures 14, 18, 19) - - 186 ns turn-on delay time t d(on) -9-ns rise time t r - 115 - ns turn-off delay time t d(off) -19-ns fall time t f -34-ns turn-off time t off - - 80 ns switching specifications (v gs = 10v) turn-on time t on v dd = 10v, i d = 20a v gs = 10v, r gs = 27 ? (figures 15, 18, 19) - - 150 ns turn-on delay time t d(on) -5.3- ns rise time t r -95-ns turn-off delay time t d(off) -37-ns fall time t f -33-ns turn-off time t off - - 105 ns gate charge specifications total gate charge at 10v q g(tot) v gs = 0v to 10v v dd = 10v, i d = 16a, i g(ref) = 1.0ma, (figures 13, 16, 17) - 10.7 13 nc total gate charge at 5v q g(tot) v gs = 0v to 5v - 5.7 6.9 nc threshold gate charge q g(th) v gs = 0v to 1v - 0.5 0.6 nc gate to source gate charge q gs -1.7-nc gate to drain ? miller ? charge q gd -2.2-nc capacitance specifications input capacitance c iss v ds = 20v, v gs = 0v, f = 1mhz (figure 12) - 470 - pf output capacitance c oss - 350 - pf reverse transfer capacitance c rss -50-pf source to drain diode specifications parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 20a - - 1.25 v i sd = 10a - - 1.0 v reverse recovery time t rr i sd = 16a, di sd /dt = 100a/ s--33ns reverse recovered charge q rr i sd = 16a, di sd /dt = 100a/ s--30nc huf76009p3, huf76009d3s
?2004 fairchild semiconductor corporation huf76009p3, huf76009d3s rev. b1 typical performance curves figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. peak current capability t a , ambient temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 0 5 10 15 20 25 25 50 75 100 125 150 i d , drain current (a) t c , case temperature ( o c) v gs = 10v v gs = 5v 0.1 1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 0.01 2 t, rectangular pulse duration (s) z jc , normalized single pulse notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 duty cycle - descending order 0.5 0.2 0.1 0.05 0.01 0.02 thermal impedance 10 100 10 -5 500 10 -4 10 -3 10 -2 10 -1 10 0 10 1 i dm , peak current (a) t, pulse width (s) transconductance may limit current in this region t c = 25 o c i = i 25 150 - t c 125 for temperatures above 25 o c derate peak current as follows: v gs = 10v v gs = 5v huf76009p3, huf76009d3s
?2004 fairchild semiconductor corporation huf76009p3, huf76009d3s rev. b1 figure 5. forward bias safe operating area figure 6. transfer characteristics figure 7. saturation characteristics figure 8. drain to source on resistance vs gate voltage and drain current figure 9. normalized drain to source on resistance vs junction temperature figure 10. normalized gate threshold voltage vs junction temperature typical performance curves (continued) 1 10 100 110 50 200 100 s 10ms 1ms v ds , drain to source voltage (v) i d , drain current (a) limited by r ds(on) area may be operation in this t j = max rated t c = 25 o c single pulse 0 10 20 30 40 2345 i d , drain current (a) v gs , gate to source voltage (v) pulse duration = 80 s duty cycle = 0.5% max v dd = 15v t j = 150 o c t j = 25 o c t j = -55 o c 0 10 20 30 40 0123 i d , drain current (a) v ds , drain to source voltage (v) v gs = 3v v gs = 4v pulse duration = 80 s duty cycle = 0.5% max v gs = 3.5v t c = 25 o c v gs = 5v v gs = 10v v gs = 4.5v 10 20 30 40 50 60 246810 i d = 5a v gs , gate to source voltage (v) r ds(on) , drain to source on resistance (m ? ) pulse duration = 80 s duty cycle = 0.5% max t c = 25 o c i d = 16a i d = 10a 0.6 0.8 1.0 1.2 1.4 1.6 -80 -40 0 40 80 120 160 normalized drain to source t j , junction temperature ( o c) on resistance v gs = 10v, i d = 20a pulse duration = 80 s duty cycle = 0.5% max 0.6 0.8 1.0 1.2 -80 -40 0 40 80 120 160 normalized gate t j , junction temperature ( o c) v gs = v ds , i d = 250 a threshold voltage huf76009p3, huf76009d3s
?2004 fairchild semiconductor corporation huf76009p3, huf76009d3s rev. b1 figure 11. normalized drain to source breakdown voltage vs junction temperature figure 12. capacitance vs drain to source voltage note: refer to fairchild application notes an7254 and an7260. figure 13. gate charge waveforms for constant gate current figure 14. switching time vs gate resistance figure 15. switching time vs gate resistance typical performance curves (continued) 0.9 1.0 1.1 1.2 -80 -40 0 40 80 120 160 t j , junction temperature ( o c) normalized drain to source i d = 250 a breakdown voltage 100 1000 0.1 1 10 20 2000 50 c, capacitance (pf) v ds , drain to source voltage (v) v gs = 0v, f = 1mhz c iss = c gs + c gd c oss ? c ds + c gd c rss = c gd 0 2 4 6 8 10 036912 v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 10v i d = 16a i d = 10a waveforms in descending order: i d = 5a 0 25 50 75 100 125 150 0 1020304050 switching time (ns) r gs , gate to source resistance ( ? ) v gs = 5v, v dd = 10v, i d = 16a t r t f t d(on) t d(off) 0 20 40 60 80 100 0 1020304050 switching time (ns) r gs , gate to source resistance ( ? ) v gs = 10v, v dd = 10v, i d = 20a t r t d(on) t f t d(off) huf76009p3, huf76009d3s
?2004 fairchild semiconductor corporation huf76009p3, huf76009d3s rev. b1 test circuits and waveforms figure 16. gate charge test circuit figure 17. gate charge waveforms figure 18. switching time test circuit figure 19. switching time waveform r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 1v q g(tot) v gs = 5v q g(tot) v gs = 10v v ds v gs i g(ref) 0 0 q gs q gd v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 huf76009p3, huf76009d3s
?2004 fairchild semiconductor corporation huf76009p3, huf76009d3s rev. b1 pspice electrical model .subckt huf76009p3 2 1 3 ; rev 16 march 2000 ca 12 8 5.6e-10 cb 15 14 5.0e-10 cin 6 8 4.5e-10 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 25.9 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1.0e-9 lgate 1 9 4.6e-9 lsource 3 7 4.7e-9 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 1.0e-3 rgate 9 20 4.0 rldrain 2 5 10 rlgate 1 9 46 rlsource 3 7 47 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 1.4e-2 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*70),3))} .model dbodymod d (is = 3.4e-13 rs = 1.0e-2 trs1 = 2e-3 trs2 = 8e-7 cjo = 1.05e-9 tt = 1.18e-8 xti = 5 m = 0.42) .model dbreakmod d (rs = 1.3e-1 trs1 = 0 trs2 = 0) .model dplcapmod d (cjo = 3.2e-10 is = 1e-30 n = 10 m = 0.6) .model mmedmod nmos (vto = 2.38 kp = 12 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rs = 0.03 rg = 4) .model mstromod nmos (vto = 2.87 kp = 28 lambda = 0.02 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 1.95 kp = 0.08 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 40 rs = 0.1) .model rbreakmod res (tc1 = 9.7e-4 tc2 = 0) .model rdrainmod res (tc1 = 9.8e-3 tc2 = 2.85e-5) .model rslcmod res (tc1 = 5e-3 tc2 = 5.05e-6) .model rsourcemod res (tc1 = 1.5e-3 tc2 = 1e-6) .model rvthresmod res (tc1 = -1.48e-3 tc2 = -5e-6) .model rvtempmod res (tc1 = -1.68e-3 tc2 = 8e-7) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -4.7 voff= -2.0) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -2.0 voff= -4.7) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -1.0 voff= 0.3) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 0.3 voff= -1.0) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 huf76009p3, huf76009d3s
?2004 fairchild semiconductor corporation huf76009p3, huf76009d3s rev. b1 saber electrical model rev 16 march 2000 template huf76009p3 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 3.4e-13, rs = 1.0e-2, trs1 = 2e-3, trs2 = 8e-7, cjo = 1.05e-9, tt = 1.18e-8, xti = 5, m = 0.42) dp..model dbreakmod = (rs = 1.3e-1, trs1 = 0, trs2 = 0) dp..model dplcapmod = (cjo = 3.2e-10, isl = 10e-30, nl = 10, m = 0.6) m..model mmedmod = (type=_n, vto = 2.38, kp = 12, is = 1e-30, tox = 1, rs = 0.03) m..model mstrongmod = (type=_n, vto = 2.87, kp = 28, lambda = 0.02, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.95, kp = 0.08, is = 1e-30, tox = 1, rs = 0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.7, voff = -2.0) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.0, voff = -4.7) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.0, voff = 0.3) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.3, voff = -1.0) c.ca n12 n8 = 5.6e-10 c.cb n15 n14 = 5.0e-10 c.cin n6 n8 = 4.5e-10 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1.0e-9 l.lgate n1 n9 = 4.6e-9 l.lsource n3 n7 = 4.7e-9 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 9.7e-4, tc2 = 0 res.rdrain n50 n16 = 1.0e-3, tc1 = 9.8e-3, tc2 = 2.85e-5 res.rgate n9 n20 = 4.0 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 46 res.rlsource n3 n7 = 47 res.rslc1 n5 n51= 1e-6, tc1 = 5e-3, tc2 = 5.05e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1.4e-2, tc1 = 1.5e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -1.68e-3, tc2 = 8e-7 res.rvthres n22 n8 = 1, tc1 = -1.48e-3, tc2 = -5e-6 spe.ebreak n11 n7 n17 n18 = 25.9 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/70))** 3)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 huf76009p3, huf76009d3s
?2004 fairchild semiconductor corporation huf76009p3, huf76009d3s rev. b1 spice thermal model rev 16 march 2000 t76009 ctherm1 th 6 9.5e-4 ctherm2 6 5 2.4e-3 ctherm3 5 4 3.9e-3 ctherm4 4 3 4.3e-3 ctherm5 3 2 5.9e-3 ctherm6 2 tl 3.0e-2 rtherm1 th 6 2.0e-2 rtherm2 6 5 1.1e-1 rtherm3 5 4 2.75e-1 rtherm4 4 3 5.3e-1 rtherm5 3 2 7.1e-1 rtherm6 2 tl 7.8e-1 saber thermal model saber thermal model t76009 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 9.5e-4 ctherm.ctherm2 6 5 = 2.4e-3 ctherm.ctherm3 5 4 = 3.9e-3 ctherm.ctherm4 4 3 = 4.3e-3 ctherm.ctherm5 3 2 = 5.9e-3 ctherm.ctherm6 2 tl = 3.0e-2 rtherm.rtherm1 th 6 = 2.0e-2 rtherm.rtherm2 6 5 = 1.1e-1 rtherm.rtherm3 5 4 = 2.75e-1 rtherm.rtherm4 4 3 = 5.3e-1 rtherm.rtherm5 3 2 = 7.1e-1 rtherm.rtherm6 2 tl = 7.8e-1 } rtherm4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 th junction case huf76009p3, huf76009d3s
?2004 fairchild semiconductor corporation huf76009p3, huf76009d3s rev. b1 huf76009p3, huf76009d3s to-252aa surface mount jedec to-252aa plastic package to-252aa 16mm tape and reel b 2 e d l 3 l e b 1 b 13 a l c seating back view 2 h 1 a 1 b 3 e 1 j 1 l 1 term. 4 0.265 minimum pad size recommended for surface-mounted applications (6.7) 0.265 (6.7) 0.070 (1.8) 0.118 (3.0) 0.063 (1.6) typ 0.090 (2.3) typ plane symbol inches millimeters notes min max min max a 0.086 0.094 2.19 2.38 - a 1 0.018 0.022 0.46 0.55 4, 5 b 0.028 0.032 0.72 0.81 4, 5 b 1 0.033 0.045 0.84 1.14 4 b 2 0.205 0.215 5.21 5.46 4, 5 b 3 0.190 - 4.83 - 2 c 0.018 0.022 0.46 0.55 4, 5 d 0.270 0.295 6.86 7.49 - e 0.250 0.265 6.35 6.73 - e 0.090 typ 2.28 typ 7 e 1 0.180 bsc 4.57 bsc 7 h 1 0.035 0.045 0.89 1.14 - j 1 0.040 0.045 1.02 1.14 - l 0.100 0.115 2.54 2.92 - l 1 0.020 - 0.51 - 4, 6 l 2 0.025 0.040 0.64 1.01 3 l 3 0.170 - 4.32 - 2 notes: 1. these dimensions are within allowable dimensions of rev. b of jedec to-252aa outline dated 9-88. 2. l 3 and b 3 dimensions establish a minimum mounting surface for terminal 4. 3. solder finish uncontrolled in this area. 4. dimension (without solder). 5. add typically 0.002 inches (0.05mm) for solder plating. 6. l 1 is the terminal length for soldering. 7. position of lead to be measured 0.090 inches (2.28mm) from bottom of dimension d. 8. controlling dimension: inch. 9. revision 11 dated 1-00. 2.0mm 4.0mm 1.5mm dia. hole 8.0mm 16mm user direction of feed c l 1.75mm 330mm 50mm 13mm 22.4mm 16.4mm cover tape general information 1. 2500 pieces per reel. 2. order in multiples of full reels only. 3. meets eia-481 revision "a" specifications.
?2004 fairchild semiconductor corporation huf76009p3, huf76009d3s rev. b1 huf76009p3, huf76009d3s to-220ab 3 lead jedec to-220ab plastic package e ?p q d h 1 e 1 l l 1 60 o b 1 b 1 2 3 e e 1 a c j 1 45 o d 1 a 1 term. 4 symbol inches millimeters notes min max min max a 0.170 0.180 4.32 4.57 - a 1 0.048 0.052 1.22 1.32 - b 0.030 0.034 0.77 0.86 3, 4 b 1 0.045 0.055 1.15 1.39 2, 3 c 0.014 0.019 0.36 0.48 2, 3, 4 d 0.590 0.610 14.99 15.49 - d 1 -0.160-4.06 - e 0.395 0.410 10.04 10.41 - e 1 -0.030-0.76 - e 0.100 typ 2.54 typ 5 e 1 0.200 bsc 5.08 bsc 5 h 1 0.235 0.255 5.97 6.47 - j 1 0.100 0.110 2.54 2.79 6 l 0.530 0.550 13.47 13.97 - l 1 0.130 0.150 3.31 3.81 2 ? p 0.149 0.153 3.79 3.88 - q 0.102 0.112 2.60 2.84 - notes: 1. these dimensions are within allowable dimensions of rev. j of jedec to-220ab outline dated 3-24-87. 2. lead dimension and finish uncontrolled in l 1 . 3. lead dimension (without solder). 4. add typically 0.002 inches (0.05mm) for solder coating. 5. position of lead to be measured 0.250 inches (6.35mm) from bot- tom of dimension d. 6. position of lead to be measured 0.100 inches (2.54mm) from bot- tom of dimension d. 7. controlling dimension: inch. 8. revision 2 dated 7-97.
disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production isoplanar? littlefet? microcoupler? microfet? micropak? microwire? msx? msxpro? ocx? ocxpro? optologic ? optoplanar? pacman? fact quiet series? fast ? fastr? fps? frfet? globaloptoisolator? gto? hisec? i 2 c? implieddisconnect? rev. i9 acex? activearray? bottomless? coolfet? crossvolt ? dome? ecospark? e 2 cmos? ensigna? fact? pop? power247? powersaver? powertrench ? qfet ? qs? qt optoelectronics? quiet series? rapidconfigure? rapidconnect? silent switcher ? smart start? spm? stealth? superfet? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic ? tinyopto? trutranslation? uhc? ultrafet ? vcx? across the board. around the world.? the power franchise ? programmable active droop?

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